1. Field of the Invention
This invention relates to a sensing circuit for a dynamic random access memory (DRAM).
2. Description of The Related Art
By referring to FIGS. 1a and 1b a conventional sensing circuit for a DRAM will be described hereinbelow. In these figures, reference numerals 1 and 2 respectively denote a first and second bit lines connected to a memory cell 3; 4 a sense amplifying circuit; 5 a precharge power source; 6 a precharge switch; 7 an equalizing switch; 8 a column decode switch; 9 a pair of input/output data lines (hereunder sometimes referred to simply as I/O lines); and 10 a word line. A reading operation of the conventional circuit constructed as above described is effected by performing the following steps:
(1) First, the precharge switch 6 and the equalizing switch 7 are turned on, and then each of the bit lines 1 and 2 is connected to the precharge power source 5.
(2) Then, the precharge switch 6 and the equalizing switch 7 are turned off and thus each of the bit lines 1 and 2 is separated from the precharge power source 5.
(3) Subsequently, one of the word lines 10 is selected and thus the memory 3 is electrically connected to each of the bit lines 1 and 2.
(4) Thereafter, the sense amplifier 4 is activated and thereby each signal on the bit lines 1 and 2 is amplified.
(6) Then, the column decode switch 8 is selected and further data are outputted to the pair of I/O lines 9.
However, recent rapid increase in memory density of a DRAM has been attended with radical decrease in spacing between bit lines. Thus, coupling capacitance between contiguous bit lines tends to increase. Further, it is said that, in case of a 16M-bit DRAM and a 64M-bit DRAM which are most highly integrated DRAMs having highest memory densities obtainable now, the ratio of noises received from a contiguous bit line to all read signals from a memory cell reaches 40% or so due to the coupling capacitance thereof. Practically, as shown in FIG. 2, when the level in voltage of a read signal .DELTA.V.sub.S from the memory cell 3 to the bit lines 1, 1' or 1" is 100 milli-volt (mV), that in voltage of a noise .DELTA.V.sub.N received by the contiguous bit line 2, 2' or 2" having a reference electric potential is 40 mV or so. Thus, the level of the read signal .DELTA.V.sub.S is lowered by that of the noise .DELTA.V.sub.N to a level of an effective read signal .DELTA.V. For example, in case of a pair (1) of the bit lines 1 and 2, the level of the effective read signal .DELTA.V.sub.1 is obtained from the levels of the read signal .DELTA.V.sub.S1 and the noise .DELTA.V.sub.N1 as follows: EQU .DELTA.V.sub.1 =.DELTA.V.sub.S1 -.DELTA.V.sub.N1 =100-40(mV)=60(mV).
Further, in case of a pair (2) of the bit lines 1' and 2', the level of the effective read signal .DELTA.V.sub.2 is obtained from the levels of the read signal .DELTA.V.sub.S2 and the noise .DELTA.V.sub.N2 as follows: EQU .DELTA.V.sub.2 =.DELTA.V.sub.S2 -.DELTA.V.sub.N2 =100+40(mV)=140(mV).
Moreover, in case of a pair (3) of the bit lines 1" and 2", the level of the effective read signal .DELTA.V.sub.3 is obtained from the levels of the read signal .DELTA.V.sub.S3 and the noise .DELTA.V.sub.N3 as follows: EQU .DELTA.V.sub.3 =-(.DELTA.V.sub.S3 -.DELTA.V.sub.N3)=-(100-40) (mV)=-60(mV).
Thus, the conventional sensing circuit has a drawback that an operating margin of the sense amplifier 4 connected to the pair of the bit lines 1 and 2 and to that of the bit lines 1" and 2" decreases.
In addition, as shown in FIG. 3, when the sense amplifier 4 is activated, the value of the difference .DELTA.V in electrical potential between the bit lines of a pair rather differs from pair to pair owing to the interference noises previously described. Thus, the signals on the bit lines 1' and 2' of the pair (2) having an originally large difference .DELTA.V in electric potential as above described are amplified faster than in cases of the other pairs (1) and (3). In contrast, the signals on the bit lines 1-2 of 1"-2" of the pair (1) or (3) having an originally small difference .DELTA.V in electric potential as above described are amplified slower than in case of the pair (2). Moreover, the amplification of the signal on the bit lines 1-2 or 1"-2" of the pair (1) or (3) having an originally small diference .DELTA.V becomes further delayed under the influence of the interference noises from the bit lines 1' and 2' of the pair (2). Thus, the conventional sensing circuit has drawbacks that access time becomes considerably large and a malfunction is liable to occur.
Further, the foregoing drawbacks of the conventional sensing circuit for a DRAM will become more serious in view of further rapid increase in memory density and in the degree of integration thereof in the future.